This invention relates to the field of switching of electrical signals, especially large numbers of such signals.
In switching a large number of inputs to any of a large number of outputs, one can reduce the number of switches required through the use of multiplexers (also known as parallel-to-serial (P/S) converters) and demultiplexers (also called serial-to-parallel (S/P) converters). Examples of circuits which use multiplexers to reduce the number of cross-points include U.S. Pat. Nos. 4,064,360 and 4,878,215. The basic process explained in the cited patents includes the steps of converting a multi-signal input into a single-signal format, switching the single signal in a switching matrix, and converting the output of the switching matrix back into a multi-signal format. This specification hereby incorporates by reference the disclosures of the above-cited patents.
One can divide non-blocking matrix switching systems into two main categories. The first category includes the "unconditionally non-blocking" switches. In an unconditionally non-blocking switch, one never needs to rearrange existing circuit connections when establishing subsequent connections. In an unconditionally non-blocking switch, all existing connections remain intact, regardless of whether one adds further connections. The second category, called "rearrangeably non-blocking" includes those switches in which one may need to alter the matrix switching configuration when adding subsequent connections, in order to preserve the integrity of the connections previously made.
FIG. 1 provides an example of an unconditionally non-blocking switching system of the prior art. The system of FIG. 1 essentially corresponds to the arrangement disclosed in the above-cited patents. One or more multiplexers convert incoming parallel signals into serial form, and the circuit redirects the serial signal, as necessary, using a single-stage non-blocking crosspoint matrix switch. One or more demultiplexers then convert the switched serial signal back to parallel form. As indicated in FIG. 1, one can have any integral number N of multiplexers and demultiplexers. Regardless of the value of N, the system remains unconditionally non-blocking, so that one may establish subsequent connections without disturbing or changing existing connections.
FIG. 2 provides an example of another switching system of the prior art. In this example, the outputs of the multiplexers feed signals to a plurality of input submatrices 100, and the demultiplexers take their inputs from the outputs of a plurality of output submatrices 101. A plurality of middle submatrices 102 stand between the input and output submatrices. A paper by Charles Clos, entitled "A Study of Non-Blocking Switching Networks", appearing in The Bell System Technical Journal, March, 1953, showed that for signal lines having M input lines and M output lines, one can guarantee that the arrangement of FIG. 2 will provide an unconditionally non-blocking switching system if one has at least 2n-1 middle submatrices, where n=M.sup.1/2.
FIG. 3 shows an example of a rearrangeably non-blocking matrix switching system. A description of such systems appears in the paper by M. C. Paull, entitled "Reswitching of Connection Networks", appearing in The Bell System Technical Journal, May, 1962. Matrix switching systems of this type include input, middle, and output stages, as shown. When one needs to rearrange existing connections to make a subsequent connection, one changes the connection path through the middle matrices.
FIG. 4 shows the use of a Paull-type matrix switching system with multiplexers and demultiplexers. FIG. 4 shows only one input matrix 110, one output matrix 112, and two middle matrices 115 and 116, but one could have more matrices, in general, as shown in FIG. 3.
The Paull-type matrix system of FIG. 4 requires even fewer cross-points, for a given size of matrix, than do the arrangements of FIGS. 1 or 2. However, the arrangement of FIG. 4 has the disadvantage that noise spikes occur when rearranging a connection path through the middle matrices. These noise spikes result from differences in signal path lengths between the various switching elements, which differences cause signal propagation delays.
Noise spikes in the signal path between the multiplexer and demultiplexer are especially problematic because the demultiplexer measures the time between successive transitions to determine whether the information being transmitted is a binary "one" or a "zero". A noise spike adds transitions to the signal. Thus, the noise spikes cause false data to enter the demultiplexers, thus reducing the reliability and efficiency of the system. In general, it is far better to delay slightly the time when a received transition occurs than to introduce an erroneous pulse, since most demultiplexers are designed to accommodate slight variations in pulse width.
The present invention provides a circuit which overcomes the problem associated with the Paull-type rearrangeably non-blocking matrix switching system. The present invention makes it practical to combine the concept of multiplexing and demultiplexing with the concept of the rearrangeably non-blocking matrices described in the article by Paull. Thus, a switching system according to the present invention enjoys the dual advantages of accurate signal transmission and reduced numbers of required crosspoint switches.